A digital signal processing circuit is suitably used for recording and reproducing a digital signal at high velocity in a digital signal recording and reproducing apparatus such as a digital audio tape recorder (DAT).
A general description of a digital signal flow when recording it in a conventional DAT will be made with reference to FIG. 6. A digital audio interface format decoder (DAIF decoder) 51 serves to decode a digital audio interface format signal (DAIF decoder) s.sub.51 fed based on digital audio interface format (DAIF). Digital data (D data) S.sub.52 formed by being digitized at a sampling frequency Fs included in the DAIF signal S.sub.51 and at quantization bit number n bits is output to a signal processing circuit 52 at predetermined timing synchronizing with the generation clock. The decoder 51 may include a PLL circuit (phase locked loop circuit) 51.sub.1 which accompanies a generation clock of frequencies 128 Fs synchronizing with a self clock of the DAIF signal S.sub.51. The PLL circuit 51.sub.1 supplies a control clock group S.sub.53, formed by dividing the generation clock, to the signal processing circuit 52. The control clock group S.sub.53 includes a system clock of 128 Fs necessary for signal processing, a Left-Right clock (LRCK) of frequency Fs indicating a channel of the D data s.sub.52 being output, a word clock (WCK) of frequency 2Fs indicating an output timing and a bit clock (BCK) of the data S.sub.52 of frequency 64Fs.
The signal processing circuit 52 sequentially signal-processes the D data S.sub.52 at a timing synchronizing with the input control clock group S.sub.52.
Signal-processing by the signal processing circuit 52 together with a RAM (random access memory) 53 includes interleaving, adding an error correcting code, 8-10 modulating and generating an ATF (Automatic Track Following) signal. Although the detailed description of such signal-processing will be omitted, an RF-REC signal s.sub.55 output from the signal processing circuit 52 is made a signal based on a track format of the DAT. A head amplifier 55 sequentially and selectively supplies current signals based on the RF-REC signal S.sub.55 to plus-azimuth and minus-azimuth heads A and B, respectively which are disposed in a manner faced to a periphery of a rotary drum 56.
It Will be noted that a DAT tape 57 is wound on the rotary drum 56 while a winding angle of 90 degrees is maintained.
Furthermore, the signal processing circuit 52 supplies a reference pulse signal S.sub.54 for PLL-controlling the rotary drum 56 to a servo circuit 54. The servo circuit 54 receives the reference pulse signal S.sub.54 and a rotation signal S.sub.57 generated in synchronization with a rotation of the rotary drum 56 to control a drive motor 56.sub.1 for the rotary drum 56 at predetermined rotation frequency fd so that the phases synchronize with each other. A rotation signal S.sub.56 for a capstan motor 60 for driving a capstan 59 which serves to transfer a tape 57 together with a pressure roller 58 is monitored and the capstan motor 60 is PLL-controlled at a predetermined tape transfer velocity so as to synchronize with the reference pulse signal S.sub.54.
Also, the signal processing circuit 52 receives the rotation signal S.sub.57 for the rotary drum 56 and intermittently supplies the RF-REC signal S.sub.55 corresponding to two tracks while the rotary drum 56 rotates by one revolution at timing synchronizing with the rotation signal S.sub.57. Thus, it will be noted that recording patterns of two tracks are formed by the respective heads A and B on the tape 57 at its predetermined position.
At a standard mode time of the DAT, the transmission rate of the D data of the DAIF signal S.sub.51 is 192 kbites/second, the rotation frequency fd of the rotary drum 56 is 2000 r.p.m. and the tape transfer velocity Vp is 8.15 mm/second.
In such a DAT construction, it will be possible for doubling a recording velocity so that the transmission rate of the D data becomes 384 kbites/second which is twice as much as that of the standard mode time while the velocities at which all the processes by the signal processing circuit 52 is made are doubled, and that the rotation frequency fd of the rotary drum 56 and the tape transfer velocity Vp are doubled, respectively.
However, the signal processing circuit 52 is required to make enormous signal processes and as a result it is substantially impossible that the process velocity of the signal processing circuit is so set as to be doubled. This prevents the digital recording and reproducing apparatus from dubbing at higher velocity.